The present invention pertains generally to testing of digital electronic systems, and more particularly to a method for reducing stored patterns for integrated circuit test by embedding built-in-self-test circuitry for chip logic into a scan test access port.
As the complexity of integrated circuits (ICs) increases, so does the cost of testing the circuits during process and manufacture. As a result, integrated circuit chips are increasingly designed using a process commonly referred to as Design For Testability (DFT). Under the DFT model, integrated circuits are designed to include on-chip testing hardware to allow manufacturing testers to apply external tests to the chip and/or to allow internal tests to execute within the chip to verify the proper functionality of the chip. The goal is to balance the amount of the on-chip testing hardware with the costs of external test equipment and the amount of time and cost required to generate effective tests and detect or isolate faults such that the overall costs due to the additional on-chip testing hardware is reduced.
One well-known DFT technique is called scan testing. Scan testing requires the use of a set of scan registers, each of which possesses both serial- and parallel-load capability. In a typical scan test, a set of scan registers is connected in series. Such a set of serially connected scan registers is referred to herein as a scan path. Input data is loaded serially (xe2x80x9cshiftedxe2x80x9d) into each of the scan registers via a Test Access Port (TAP). Once the input data is loaded, the contents of the scan registers are driven into the circuit under test (CUT) in parallel and the CUT is instructed to execute one or more clock cycles. The output of the CUT after execution of the one or more clock cycles is then captured in parallel into the scan registers and shifted serially out under control of the TAP.
One form of scan testing is known as boundary scan. In boundary scan, each of the scan registers is coupled between an I/O pin of the CUT and circuitry internal to the CUT. During a boundary scan test, the scan registers therefore replace the I/O pins of the IC for loading and receiving data.
Scan testing is advantageous for several reasons. First, scan test allows a high degree of controllability and observability of signals inside the chip. Any set of data inputs can be shifted into a given scan path and applied to the CUT, and the CUT may be allowed to execute for any controlled number of clock cycles before the output is observed. Scan paths may be fully integrated (meaning that a scan register is substituted for each functional register in a given data path) or isolated (meaning that the scan register is not in the normal data path). This gives the designer of the IC flexibility in determining which portions of the CUT warrant special on-chip testing hardware. In addition, because the scan registers are loaded via a serial TAP, test data can be input to the CUT via a single serial data line rather than by applying a tester channel (e.g., a bed-of-nails tester) to each I/O pin or test node of the CUT. This significantly reduces tester configuration and setup costs and ensures that no pin-to-pin data interference occurs.
As just described, scan testing requires the use of a TAP and a serial communications protocol for controlling the shifting in of test stimulus, test execution, and shifting out of test response data. The TAP architecture and TAP communications protocol has been standardized in the well-known IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture [IEEE 1989].
FIG. 1 is a block diagram of the chip architecture for the IEEE 1149.1 standard. As shown, a chip (or board) 10 implemented according to the standard includes coupled via a plurality of scan cells 50a, 50b, . . . 50p coupled between chip specific application logic 74a-74d (interconnections not shown) and a plurality of input and/or output (I/O) pads 52a, 52b, . . . , 52p. Chip 10 includes a TAP circuit block 20 having a test data in (TDI) port 22, a test mode select (TMS) port 24, a test clock (TCK) port 26, and a test data out (TDO) port 28. TAP circuit block 20 includes an instruction register 32, a bypass register 34, and optionally one or more miscellaneous registers 36, each coupled between the TDI input and the input of a multiplexer 38. Boundary scan cells 50a, 50b, . . . 50p are connected in series between the test data in TDI input and an input of multiplexer 38. TAP circuit block 20 also includes a scan-in port Si 80 and one or more scan-out port So 82, discussed hereinafter. Scan-in port 80 is coupled to the TDI port 22; scan-out port(s) 82 are coupled to an input of multiplexer 38. Multiplexer 38 is programmable to select one of its inputs, including the instruction register 32, the bypass register 34, one of the miscellaneous registers 36, (one of) the scan-out port(s) 82, or the output of the boundary scan chain 50 (i.e., the contents of scan cell 50p), for output onto the TDO port 28. TMS port 24 and TCK port 26 are coupled to a TAP controller 30 (which implements a finite state machine FSM 31). The current state of the TMS signal, in combination with its past states, determines the operation of the TAP 20. Test clock signal TCK is used to synchronize input of the mode select signal TMS and test data in signal TDI into the TAP. Test mode select signal TMS controls the finite state machine implemented in the TAP controller 30 which controls whether the TAP 20 accepts test data or instructions.
Scan testing is not limited to boundary scan (implemented in FIG. 1 by scan path 50), where the scan path includes scan cells only at the I/O pins. Scan paths may be implemented anywhere on the chip where a set of data storage cells exist. Since integrated circuits are often implemented modularly (i.e., where the integrated circuit functions are divided into a set of separate logic blocks) multiple internal scan paths may be implemented around each logic block to test each logic block independently of the other logic blocks. FIG. 1 illustrates the implementation of multiple internal scan paths 72a, 72b, 72c, and 72d. Each scan path implements a set of interconnected scan cells (not shown) corresponding to a set of data storage cells in a respective logic block 74a-74d. Since each logic block is independent of the others, the number of scan cells in each scan path 72a, 72b, 72c, 72d may vary. Also, since each scan path 72a, 72b, 72c, 72d is independent of the others, a single scan-in input Si 80 may be fed into each scan path without affecting the randomness of the test pattern suite applied to any given scan path. During a scan test, the TAP shifts data in from the TDI port 22 along the scan-in Si 80 path and into each scanpath[0 . . . n] 72a, 72b, 72c, 72d. The number of bits shifted into the scan paths 72a-72b via the scan-in port Si 80 is equivalent to the number of scan cells in the longest scan path 72a, 72b, 72c, or 72d. Alternatively, each scan path can be loaded one at a time with exactly the number of bits in that scan chain.
In operation, an instruction is clocked in serially from the TDI port 22 into instruction register 32. Test controller 30 responds to the instruction by configuring the test circuitry according to the instruction (e.g., selecting the input of the scan cells to come from their serial inputs via the scan chain rather than their parallel inputs via the I/O pads, or selecting the multiplexer 38 input). Each instruction enables a single serial test data register path between TDI and TDO. The instruction is then executed under the control of the TAP controller 30 (e.g., shifting data serially into or out of the scan cells in synchronization with the test clock TCK signal).
Another well-known manufacturing testing technique is called Built-In-Self-Test (BIST). The BIST technique also employs dedicated on-chip test circuitry, shown in FIG. 1 at 60, to enable an integrated circuit chip to perform self-testing, usually with only minimal assistance (such as the provision of power 7, clock 8, and reset 9 signals) from an external tester 5 or a board or a system.
BIST can include many forms of testing, each executing with minimal external assistance (e.g., using only externally provided power and clocking signals). One form of BIST is known as concurrent online testing that occurs simultaneously with normal functional operation, such as duplication and comparison. Another BIST form is known as non-concurrent online testing that occurs when the system is in an idle state, such as execution of diagnostic routines. Yet another form of BIST is known as offline testing. Off-line BIST, which is the context of the invention, occurs when the system is placed in a special test mode.
BIST circuitry has often been employed with certain special classes of circuits, most notably around regular memory array structures like Random Access Memory (RAM). BIST applied to memory structures is often referred to as MBIST. The extension of BIST techniques to general chip logic structures (i.e., logic gates) has been applied, especially in the area of scan testing, and is herein referred to as logic BIST, or LBIST. Off-line LBIST is applied to blocks of combinational logic interconnected by storage cells. BIST circuitry includes test pattern generators 62, output response analyzers 64, a distribution system including busses, multiplexers, and scan paths 72a, 72b, 72c, 72d for transmitting data from the test pattern generators 62 to the logic blocks under test (LBUTs) 74a, 74b, 74c, 74d and from the LBUTs to the output response analyzers 64, and a BIST controller 6 which controls the BIST circuitry and circuit under test during self-test. The BIST controller 6 can be implemented in the integrated circuit tester 5 off chip or can be implemented adjacent to the logic block designated for LBIST. The BIST controller controls the stepping of the LBUTs 74a-74d through a test program, controls the BIST test clocks 8, controls the configuration of the data paths throughout the CUT, and controls the shifting of data in and out of the various scan paths 72a-72d. 
Effective BIST depends on the generation of effective test patterns. Test pattern generation is the topic of extensive research. Effective known testing includes exhaustive testing, pseudo-random testing, and pseudoexhaustive testing. Exhaustive tests apply every possible input to the circuit under test. For example, in an n-input m-output combinatorial circuit, this requires the application (and storage in the IC tester) of 2n inputs. For a circuit with a large number of inputs, the storage requirements render this technique impractical. Furthermore, exhaustive testing does not detect faults that occur due to the sequential behavior of the circuit.
In pseudoexhaustive testing, a circuit under test is segmented into a set of sub-circuits, each of which receives a smaller subset m of the total set n of inputs (i.e., m less than n). This reduces the number of test patterns from 2n to 2m for a given subcircuit.
Pseudorandom testing involves the application of a reduced set of test patterns, seemingly random, that are actually algorithmically generated from a starting seed; accordingly, the test pattern is deterministic, which allows the test pattern to be identically regenerated from a known seed. Pseudorandom testing is popular due to the reduction in test patterns required to be stored in the IC tester while still providing high fault coverage; in addition, with proper clock control, pseudorandom testing can be used to effectively identify faults that occur due to sequential behavior of the circuit.
Each of the test pattern generation techniques described above makes extensive use of linear feedback shift registers (LFSRs). In addition, with scan techniques, extensive use of signature registers (i.e., output compression) is made in order to simplify the verification of the serial output from the scan paths. A more detailed discussion of test pattern generation, scan, and BIST techniques may be found in Abramovici et al., xe2x80x9cDigital Systems Testing and Testable Designxe2x80x9d, IEEE Press (1990), ISBN 0-7803-1062-4, pp. 343-489, which is incorporated herein by reference for all that it teaches.
BIST applied to combinational logic structures in an integrated circuit is problematic due to the large percentage of BIST circuit overhead as compared with the percentage of the actual circuit under test (CUT) being tested. A common compromise is to use BIST only around dense memory arrays and to use another test scheme (usually full scan) for the remainder of the chip logic.
As integrated circuits grow in size and complexity, the size of the scan test pattern set grows proportionally. The entire set of patterns, both stimulus and response, must be stored in a digital IC tester. A substantial majority of these test patterns consists of randomly selected binary values used as xe2x80x9cfillerxe2x80x9d, so named because they are required to xe2x80x9cfillxe2x80x9d the entire scan path, around a relatively small number of explicitly specified bits. These random fill bits are actually quite useful in detecting many defects and therefore cannot be dispensed with; however, random fill bits are not of sufficient complexity to warrant storage in the limited tester memory if another method of deriving them could be found. Accordingly, a need exists for a technique for reducing the IC tester costs in terms of both hardware and complexity. A need also exists for a technique for reducing the test circuit overhead in integrated circuits without reducing the DFT and BIST functionality on the chip.
The present invention is a novel method and apparatus for reducing IC tester complexity and hardware while simultaneously reducing the test circuit overhead in integrated circuits without compromising the DFT and BIST functionality. In accordance with the invention, an integrated circuit includes a test access port (TAP) and DFT scan circuitry. The TAP includes all the functionality required for a BIST environment within the TAP block itself, including a linear feedback shift register (LFSR), a multiple input signature register (MISR), a step counter, a shift counter, a step/shift controller, and a MISR mask register. With the addition of these elements, the need for a separate BIST module within the integrated circuit is essentially eliminated because BIST test patterns can be automatically generated using the tap circuitry and simultaneously loaded into multiple parallel scanpaths throughout the digital circuit. Because the BIST essentially utilizes existing test hardware already available on the chip, namely the TAP and the scan paths, there is no need for a separate BIST controller for controlling the generation and execution of the BIST routines. Furthermore, the tester hardware used for storing and downloading random fill test patterns in the IC tester is eliminated.
In accordance with the invention, the TAP module includes a shift register coupled in parallel with the scan-in input Si between the scan-data-in (SDI) port and the scan-in input Si. At the scan-out output So, a multiple input signature register (MISR), which is preferably maskable, is coupled between the scan-out output So and the scan-data-out (SDO) port. When it is desired to execute BIST, a test mode select TMS signal instructs the TAP controller to receive an instruction, which instructs the TAP to select the LSFR path for incoming data and to select the MISR path for outgoing data. This allows the tester to instruct the TAP to generate patterns using the LFSR, while simultaneously compressing the outgoing data from So. A shift counter may be included to allow the tester to specify the number of bits to shift in from the LFSR to the scan paths SCANPATH[0:n]. The tester simply loads a number between 1 and the length of the longest scan chain into the shift counter, and the TAP controller shifts one bit per clock cycle as the shift counter decrements once per clock cycle, repeating this process until the counter counts down to zero. A step counter allows the tester to specify the number of clock cycles to execute once the data is shifted into all the scan chains. Alternatively, or in addition, to the shift and step counters, a step/shift controller may be used to program a sequence of steps and shifts.